1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory and a method for manufacturing the same, and more specifically to an improved structure of a non-volatile semiconductor memory of a floating gate type capable of storing multi-value information.
2. Description of Related Art
A floating gate transistor has been well known as a programmable and erasable non-volatile memory cell. This floating gate transistor generally includes a source region and a drain region formed in a surface region of a semiconductor substrate, separately from each other, to form a channel region between the source region and the drain region. On this channel region, there are formed a first insulator film, a floating gate, a second insulator film and a control gate in the named order.
In the floating gate transistor, ordinarily, a first level gate electrode (floating gate) is formed on a silicon nitride film formed on a principal surface of the semiconductor substrate, and an interlayer insulator film composed of a silicon oxide film and a silicon nitride film is formed on the first gate electrode, and then, a second level gate electrode (control gate) is formed on the interlayer insulator film.
In this construction, an electric charge for non-volatile stored information is stored in the floating gate formed of the first level gate electrode. Here, the information electric charge is written by injecting electrons into the floating gate electrode from the semiconductor substrate, and the information electric charge is erased by discharging or extracting electrons from the floating gate electrode into the semiconductor substrate.
In this type of non-volatile memory, the difference of a threshold caused by the difference in an electric charge storing condition of the floating gate is memorized as data "0" or data "1". Namely, a bit of information is memorized in the floating gate.
In a non-volatile semiconductor memory composed of floating gate transistors as mentioned above, it has become important to elevate an integration density. Under this demand, Japanese Patent Application Pre-examination Publication No. JP-A-5-082728, (the content of the which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-5-082728 is available from the Japanese Patent Office and the content of the English abstract of JP-A-5-082728 is also incorporated by reference in its entirety into this application) proposes a non-volatile semiconductor memory including a floating gate transistor having a thin film transistor structure.
Now, the non-volatile semiconductor memory having the thin film transistor structure will be described with reference to FIG. 1, which is a diagrammatic section view of the floating gate transistor of this non-volatile semiconductor memory.
As shown in FIG. 1, on a semiconductor substrate 101, an interlayer insulator film 102 is formed, and a semiconductor thin film 103 is formed on the interlayer insulator film 102. A pair of source/drain regions 103 and a channel region 103b are formed in the semiconductor thin film 103. Furthermore, a first level insulator film 104 is formed to cover a surface of the channel region 103b, and a floating gate electrode 105 is formed on the first level insulator film 104 to extend over the channel region 103b.
Furthermore, a second level insulator film 106 is formed to cover the floating gate electrode 105, and a control gate electrode 107 is formed on the second level insulator film 106 to extend over the floating gate electrode 105. The control gate electrode 107 is covered with an insulator film 108.
In order to further elevate the integration density of the above mentioned non-volatile memory, it is attempted to reduce a size of the floating gate electrode and a spacing between memory cells. However, this reduction of the semiconductor device size is dependent upon a degree of patterning precision in a photolithography and in a dry etching.
In a reduction projection exposure which is ordinarily used, however, the degree of patterning precision in the photolithography is limited by resolution. Therefore, microminiaturization of the floating gate transistor has a limit, and therefore, elevation of the integration density of the non-volatile memory has a limit.
Furthermore, in the prior art, it is possible to form another floating gate transistor having the thin film transistor as mentioned above, on an interlayer insulator film formed on the floating gate transistor formed on the surface of the semiconductor substrate. This structure can elevate the integration density of the non-volatile memory. In this structure, however, a memory cell region of the non-volatile semiconductor memory projects in the form of a convex, and becomes higher than the other region on the semiconductor chip, with the result that the degree of planarization is deteriorated. Furthermore, unevenness of focus occurs in an exposure step of the photolithography. As a result, microfabrication of the floating gate transistor becomes difficult.
As mentioned above, in the prior art structure, the integration density of the non-volatile memory is limited by a minimum dimension determined by a manufacturing process attributable to the structure, and therefore, it is not possible to further elevate the integration density.